The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD ); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; a first resistance switching element (202) coupled between said first storage node and a first access line (BL); and a second resistance switching element (204) coupled between said second storage node and a second access line (BLB).