Cellule mémoire volatile et non volatile combinée

Abstract : The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD ); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; a first resistance switching element (202) coupled between said first storage node and a first access line (BL); and a second resistance switching element (204) coupled between said second storage node and a second access line (BLB).
Type de document :
Brevet
France, N° de brevet: FR 2970591 (A1) WO/2012/098182 (A1). 2012, pp.N/A
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00861514
Contributeur : Isabelle Gouat <>
Soumis le : jeudi 12 septembre 2013 - 19:12:59
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00861514, version 1

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Citation

Yoann Guillemenet, Lionel Torres. Cellule mémoire volatile et non volatile combinée. France, N° de brevet: FR 2970591 (A1) WO/2012/098182 (A1). 2012, pp.N/A. 〈lirmm-00861514〉

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