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Éléments de mémoire non-volatile

Abstract : The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00861517
Contributor : Isabelle Gouat <>
Submitted on : Thursday, September 12, 2013 - 7:32:34 PM
Last modification on : Tuesday, June 26, 2018 - 1:18:31 AM

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  • HAL Id : lirmm-00861517, version 1

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Citation

Yoann Guillemenet, Lionel Torres. Éléments de mémoire non-volatile. France, N° de brevet: FR 2976712 (A1) WO/2012/171989 (A2). 2012, pp.N/A. ⟨lirmm-00861517⟩

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