Built-In Self-Test for Manufacturing TSV Defects before bonding - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2014

Built-In Self-Test for Manufacturing TSV Defects before bonding

Abstract

In this paper we present a BIST method for TSV pre-bond testing. A dedicated test circuitry per TSV is desi gned and simulated w.r.t a variety of defects and PVT variations. Based on discharge delay evaluation, the BIST scheme supports concurrent testing, requires small-area implementation and it is robust against PVT variations.
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Dates and versions

lirmm-00989682 , version 1 (12-05-2014)

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. Built-In Self-Test for Manufacturing TSV Defects before bonding. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818771⟩. ⟨lirmm-00989682⟩
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