Built-In Self-Test for Manufacturing TSV Defects before bonding

Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1 Hakim Zimouche 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper we present a BIST method for TSV pre-bond testing. A dedicated test circuitry per TSV is desi gned and simulated w.r.t a variety of defects and PVT variations. Based on discharge delay evaluation, the BIST scheme supports concurrent testing, requires small-area implementation and it is robust against PVT variations.
Keywords : Void 3D Pre-Bond Testing BIST PVT Pin-hole TSV
Type de document :
Communication dans un congrès
IEEE. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. 32nd IEEE VLSI Test Symposium (VTS) pp.1-6, 2014, 〈10.1109/VTS.2014.6818771〉
Liste complète des métadonnées
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00989682
Contributeur : Marie-Lise Flottes <>
Soumis le : lundi 12 mai 2014 - 11:38:51
Dernière modification le : mardi 23 octobre 2018 - 10:46:02

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SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER | TEST

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. Built-In Self-Test for Manufacturing TSV Defects before bonding. IEEE. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. 32nd IEEE VLSI Test Symposium (VTS) pp.1-6, 2014, 〈10.1109/VTS.2014.6818771〉. 〈lirmm-00989682〉

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