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Built-In Self-Test for Manufacturing TSV Defects before bonding

Giorgio Di Natale 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1 Hakim Zimouche 1 
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper we present a BIST method for TSV pre-bond testing. A dedicated test circuitry per TSV is desi gned and simulated w.r.t a variety of defects and PVT variations. Based on discharge delay evaluation, the BIST scheme supports concurrent testing, requires small-area implementation and it is robust against PVT variations.
Keywords : TSV Pin-hole PVT BIST 3D Pre-Bond Testing Void
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00989682
Contributor : Marie-Lise Flottes Connect in order to contact the contributor
Submitted on : Monday, May 12, 2014 - 11:38:51 AM
Last modification on : Friday, August 5, 2022 - 10:48:18 AM

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

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Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. Built-In Self-Test for Manufacturing TSV Defects before bonding. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818771⟩. ⟨lirmm-00989682⟩

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