Built-In Self-Test for Manufacturing TSV Defects before bonding
Abstract
In this paper we present a BIST method for TSV pre-bond testing. A dedicated test circuitry per TSV is desi gned and simulated w.r.t a variety of defects and PVT variations. Based on discharge delay evaluation, the BIST scheme supports concurrent testing, requires small-area implementation and it is robust against PVT variations.