A BIST Method for TSVs Pre-Bond Test

Hakim Zimouche 1 Marie-Lise Flottes 1 Bruno Rouzeyre 1 Giorgio Di Natale 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In this paper we present a Built-In-Self-Test (BIST) method dedicated to pre-bond testing of TSVs in 3D stacked integrated circuits. The test method aims to detect full-open and pin-hole defects by measuring the discharge delay of TSVs' equivalent capacitance. The paper presents an original solution for monitoring the discharge delay of the TSV under test independently of the process variations. Simulation-based results shows that the method is robust w.r.t these variations. The proposed BIST circuitry is small enough to be inserted in the available area between the TSVs.
Type de document :
Communication dans un congrès
IDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, 2013, 〈http://idtsymposium.org/〉. 〈10.1109/IDT.2013.6727081〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00989727
Contributeur : Marie-Lise Flottes <>
Soumis le : lundi 12 mai 2014 - 12:28:00
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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Hakim Zimouche, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale. A BIST Method for TSVs Pre-Bond Test. IDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, 2013, 〈http://idtsymposium.org/〉. 〈10.1109/IDT.2013.6727081〉. 〈lirmm-00989727〉

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