Voltage Spikes on the Substrate to Obtain Timing Faults

Abstract : Fault attacks are widely deployed against secure devices by hardware evaluation centers. While the least expensive fault injection techniques, like clock or voltage glitches, are well taken into account in secure devices by dedicated hardware counter-measures, more advanced techniques, such as light based attacks, require huge investments. This paper presents a new way to induce faults at a moderate cost that may defeat already in place hardware counter-measures. To demonstrate its effectiveness we applied this technique on an ASIC component. For this demonstration, fault exploitation is operated using the classic Bell core attack applied on a modular exponentiation supported by a modular arithmetic co-processor.
Type de document :
Communication dans un congrès
DSD: Digital System Design, Sep 2013, Santander, Spain. 16th Euromicro Conference Series on Digital System Design, pp.483-486, 2013, Digital System Design (DSD). 〈10.1109/DSD.2013.146〉
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01096076
Contributeur : Philippe Maurine <>
Soumis le : mardi 16 décembre 2014 - 16:59:31
Dernière modification le : jeudi 28 juin 2018 - 17:53:17

Identifiants

Citation

Karim Tobich, Philippe Maurine, Pierre-Yvan Liardet, Mathieu Lisart, Thomas Ordas. Voltage Spikes on the Substrate to Obtain Timing Faults. DSD: Digital System Design, Sep 2013, Santander, Spain. 16th Euromicro Conference Series on Digital System Design, pp.483-486, 2013, Digital System Design (DSD). 〈10.1109/DSD.2013.146〉. 〈lirmm-01096076〉

Partager

Métriques

Consultations de la notice

69