Voltage Spikes on the Substrate to Obtain Timing Faults - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2013

Voltage Spikes on the Substrate to Obtain Timing Faults

Abstract

Fault attacks are widely deployed against secure devices by hardware evaluation centers. While the least expensive fault injection techniques, like clock or voltage glitches, are well taken into account in secure devices by dedicated hardware counter-measures, more advanced techniques, such as light based attacks, require huge investments. This paper presents a new way to induce faults at a moderate cost that may defeat already in place hardware counter-measures. To demonstrate its effectiveness we applied this technique on an ASIC component. For this demonstration, fault exploitation is operated using the classic Bell core attack applied on a modular exponentiation supported by a modular arithmetic co-processor.
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Dates and versions

lirmm-01096076 , version 1 (16-12-2014)

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Karim Tobich, Philippe Maurine, Pierre-Yvan Liardet, Mathieu Lisart, Thomas Ordas. Voltage Spikes on the Substrate to Obtain Timing Faults. DSD: Digital System Design, Sep 2013, Santander, Spain. pp.483-486, ⟨10.1109/DSD.2013.146⟩. ⟨lirmm-01096076⟩
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