2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2014

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures

Abstract

Design For Test (DFT) of 3D stacked integrated circuits based on Through Silicon Vias (TSVs) is one of the hot topics in the field of test of integrated circuits. This is due to the hard test accessibility (especially for upper dies) and to the high complexity where each die can embed hundreds of IPs. In this paper we propose a DFT architecture based on IEEE P1687 to enable the test of 3D stacked ICs. The proposed test architecture allows the test at all 3D fabrication levels: pre-, mid-, and post-bond levels. We present a test pattern retargeting flow using IEEE P1687 languages ICL (Instrument Connectivity Language) and PDL (Procedural Description Language), which allows easy retargeting from 2D (die-level) to 3D (stack-level). Compared to IEEE 1149.1 based 3D test architecture, our proposed 3D test architecture is more flexible and enhances test concurrency without an additional area cost.
Fichier principal
Vignette du fichier
2D to 3D Test Pattern Retargeting using IEEE P1687 based 3D DFT Architectures_ISVLSI_2014.pdf (293.74 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

lirmm-01119605 , version 1 (23-02-2015)

Identifiers

Cite

Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.386-391, ⟨10.1109/ISVLSI.2014.83⟩. ⟨lirmm-01119605⟩
242 View
918 Download

Altmetric

Share

Gmail Facebook X LinkedIn More