Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs

Fernanda Lima Kastensmidt 1 Jorge Tonfat 1 Thiago Hanna Both 2 Paolo Rech 1 Gilson Wirth 2 Ricardo Da Luz Reis 1 Florent Bruguier 3 Pascal Benoit 3 Lionel Torres 3 Christopher Frost 4
1 PGMICRO - PgMicro - Instituto de Informática [UFRGS]
2 UFRGS - Departamento de Engenharia Eletrica
3 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
4 ISIS - Science and Technology Facilities Council
Abstract : This work investigates the effects of aging and voltage scaling in neutron-induced bit-flip in SRAM-based Field Programmable Gate Array (FPGA). Experimental results show that aging and voltage scaling can increase in at least two times the susceptibility of SRAM-based FPGAs to Soft Error Rate (SER). These results are innovative, because they combine three real effects that occur in programmable circuits operating at ground-level applications. In addition, a model at electrical level for aging, soft error and different voltages in SRAM memory cells was described to investigate by simulation in more details the effects observed at the practical neutron irradiation experiment. Results can guide designers to predict soft error effects during the lifetime of devices operating in different power supply mode.
Keywords : Voltage and aging in FPGAs Neutron induced soft error Soft error rate in FPGAs
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Article dans une revue
Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2344-2348. 〈10.1016/j.microrel.2014.07.100〉
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Fernanda Lima Kastensmidt, Jorge Tonfat, Thiago Hanna Both, Paolo Rech, Gilson Wirth, et al.. Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs. Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2344-2348. 〈10.1016/j.microrel.2014.07.100〉. 〈lirmm-01138923〉

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