Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Journal of Circuits, Systems, and Computers Year : 2016

Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits

Abstract

This paper presents a digital Embedded Test Instrument (ETI) for on-chip phase noise testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885µm2, which represents an extremely small silicon area. Hardware measurements are performed on a FPGA prototype that validate the proposed instrument.
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Dates and versions

lirmm-01233013 , version 1 (24-11-2015)

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Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre. Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits. Journal of Circuits, Systems, and Computers, 2016, 25 (3), pp.#1640014. ⟨10.1142/S0218126616400144⟩. ⟨lirmm-01233013⟩
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