Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits

Florence Azaïs 1 Stéphane David-Grignot 2 Laurent Latorre 1 François Lefevre 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents a digital Embedded Test Instrument (ETI) for on-chip phase noise testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885µm2, which represents an extremely small silicon area. Hardware measurements are performed on a FPGA prototype that validate the proposed instrument.
Type de document :
Article dans une revue
Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 〈10.1142/S0218126616400144〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01233013
Contributeur : Florence Azais <>
Soumis le : mardi 24 novembre 2015 - 12:11:52
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre. Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits. Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 〈10.1142/S0218126616400144〉. 〈lirmm-01233013〉

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