Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits

Florence Azaïs 1 Stéphane David-Grignot 2, 1 Laurent Latorre 3 François Lefevre 2
1 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents a digital Embedded Test Instrument (ETI) for on-chip phase noise testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885µm2, which represents an extremely small silicon area. Hardware measurements are performed on a FPGA prototype that validate the proposed instrument.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01233013
Contributor : Florence Azais <>
Submitted on : Tuesday, November 24, 2015 - 12:11:52 PM
Last modification on : Monday, May 13, 2019 - 2:52:50 PM

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Florence Azaïs, Stéphane David-Grignot, Laurent Latorre, François Lefevre. Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits. Journal of Circuits, Systems, and Computers, World Scientific Publishing, 2016, 25 (3), pp.#1640014. ⟨10.1142/S0218126616400144⟩. ⟨lirmm-01233013⟩

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