A framework for efficient implementation of analog/RF alternate test with model redundancy

Syhem Larguech 1 Florence Azaïs 1 Serge Bernard 1 Mariane Comte 1 Vincent Kerzérho 1 Michel Renovell 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : A promising solution to reduce the testing costs of analog/RF circuits is the alternate test strategy, which permits to replace costly specification measurements by simple low-cost indirect measurements. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is today limited mainly because of a lack of confidence in alternate test predictions. A potential solution to improve test confidence is to exploit model redundancy. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may be applied. In this paper, we present a framework for efficient implementation of alternate test with model redundancy. Results are illustrated on a power amplifier case study for which we have experimental test data over 11,200 devices.
Type de document :
Communication dans un congrès
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. IEEE, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’15), pp.621-626, 2015, 〈10.1109/ISVLSI.2015.30〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01233104
Contributeur : Florence Azais <>
Soumis le : mardi 24 novembre 2015 - 14:47:43
Dernière modification le : jeudi 24 mai 2018 - 15:59:25

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Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. A framework for efficient implementation of analog/RF alternate test with model redundancy. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. IEEE, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’15), pp.621-626, 2015, 〈10.1109/ISVLSI.2015.30〉. 〈lirmm-01233104〉

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