A framework for efficient implementation of analog/RF alternate test with model redundancy

Syhem Larguech 1 Florence Azaïs 1 Serge Bernard 2 Mariane Comte 1 Vincent Kerzérho 2 Michel Renovell 1
1 TEST - TEST
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : A promising solution to reduce the testing costs of analog/RF circuits is the alternate test strategy, which permits to replace costly specification measurements by simple low-cost indirect measurements. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is today limited mainly because of a lack of confidence in alternate test predictions. A potential solution to improve test confidence is to exploit model redundancy. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may be applied. In this paper, we present a framework for efficient implementation of alternate test with model redundancy. Results are illustrated on a power amplifier case study for which we have experimental test data over 11,200 devices.
Keywords : analog/RF ICs specifications low-cost measurements alternate testing indirect testing test efficiency test confidence model redundancy
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01233104
Contributor : Florence Azais <>
Submitted on : Tuesday, November 24, 2015 - 2:47:43 PM
Last modification on : Wednesday, August 28, 2019 - 7:12:02 PM

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CNRS | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER | SMARTIES | TEST

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Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzérho, et al.. A framework for efficient implementation of analog/RF alternate test with model redundancy. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.621-626, ⟨10.1109/ISVLSI.2015.30⟩. ⟨lirmm-01233104⟩

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