Hardware Trojan Prevention using Layout-Level Design Approach

Abstract : Hardware Trojans (HTs) are ultimately a dangerous threat in semiconductor industry. The serious impact of HTs in security applications and global economy brings extreme importance to their detection and prevention techniques. This paper focuses on developing a HT prevention techniques through a layout level design approach. The principle is to let no available space on silicon for an attacker to insert a HT. Experiments determine the maximum occupational rate and critical empty spaces while filling with standard cells. The proposed technique makes HT insertion nearly impossible.
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Communication dans un congrès
IEEE. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. Proceedings of the 2015 European Conference on Circuit Theory and Design (ECCTD), 〈10.1109/ECCTD.2015.7300093〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01234072
Contributeur : Giorgio Di Natale <>
Soumis le : jeudi 26 novembre 2015 - 10:56:04
Dernière modification le : jeudi 28 juin 2018 - 18:44:03

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Papa-Sidy Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trojan Prevention using Layout-Level Design Approach. IEEE. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. Proceedings of the 2015 European Conference on Circuit Theory and Design (ECCTD), 〈10.1109/ECCTD.2015.7300093〉. 〈lirmm-01234072〉

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