Hardware Trojan Prevention using Layout-Level Design Approach - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2015

Hardware Trojan Prevention using Layout-Level Design Approach


Hardware Trojans (HTs) are ultimately a dangerous threat in semiconductor industry. The serious impact of HTs in security applications and global economy brings extreme importance to their detection and prevention techniques. This paper focuses on developing a HT prevention techniques through a layout level design approach. The principle is to let no available space on silicon for an attacker to insert a HT. Experiments determine the maximum occupational rate and critical empty spaces while filling with standard cells. The proposed technique makes HT insertion nearly impossible.
Fichier principal
Vignette du fichier
HTpreventionusinglayoutlevedesignapproach.pdf (586.6 Ko) Télécharger le fichier
Origin Files produced by the author(s)

Dates and versions

lirmm-01234072 , version 1 (25-07-2019)



Papa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trojan Prevention using Layout-Level Design Approach. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩. ⟨lirmm-01234072⟩
122 View
146 Download



Gmail Mastodon Facebook X LinkedIn More