3D DFT Challenges and Solutions

Abstract : Design-For-Test (DFT) of 3D stacked integrated circuits based on Through Silicon Vias (TSVs) is one of the hot topics in the field of test of integrated circuits. This is due to the test access complexity of dies' components that must be controlled/observed before and after bonding (especially for upper dies), and the high complexity of 3D systems where each die can embed hundreds of IPs. DFT of 3D circuits concerns all the components of the 3D system, including the dies and the inter-die interconnections. We address the problem of test architecture definition for both TSVs testing before bonding and cores testing before and after bonding. We present test solutions allowing to access the components under test while physical interconnects for test data propagation differ according to the stacking step. The paper also discusses core test scheduling issues.
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Communication dans un congrès
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.603-608, Proceedings of 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 〈10.1109/ISVLSI.2015.11〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01234076
Contributeur : Giorgio Di Natale <>
Soumis le : jeudi 26 novembre 2015 - 10:58:51
Dernière modification le : jeudi 28 juin 2018 - 18:44:02

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Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, et al.. 3D DFT Challenges and Solutions. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.603-608, Proceedings of 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 〈10.1109/ISVLSI.2015.11〉. 〈lirmm-01234076〉

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