Design-For-Test (DFT) of 3D stacked integrated circuits based on Through Silicon Vias (TSVs) is one of the hot topics in the field of test of integrated circuits. This is due to the test access complexity of dies' components that must be controlled/observed before and after bonding (especially for upper dies), and the high complexity of 3D systems where each die can embed hundreds of IPs. DFT of 3D circuits concerns all the components of the 3D system, including the dies and the inter-die interconnections. We address the problem of test architecture definition for both TSVs testing before bonding and cores testing before and after bonding. We present test solutions allowing to access the components under test while physical interconnects for test data propagation differ according to the stacking step. The paper also discusses core test scheduling issues.