Testing PUF-Based Secure Key Storage Circuits

Mafalda Cortez 1 Gijs Roelofs 1 Said Hamdioui 1 Giorgio Di Natale 2
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. In particular it provides the testability analysis and a secure Built-In Self-Test (BIST) solution for Fuzzy Extractor (FE) which is the main component of PUF-based systems. The scheme targets high stuck-at-fault (SAF) coverage by performing scan-chain free functional testing, to prevent scan-chain abuse for attacks. The scheme reuses existing FE sub-blocks (for pattern generation and compression) to minimize the area overhead. The scheme is integrated in FE design and simulated; the results show that a SAF fault coverage of 95.1% can be realized with no more than 50k clock cycles at the cost of a negligible area overhead of only 2.2%. Higher fault coverage is possible to realize at extra cost.
Type de document :
Communication dans un congrès
DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. pp.1-6, 2014, Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. 〈10.7873/DATE.2014.207〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01234141
Contributeur : Giorgio Di Natale <>
Soumis le : jeudi 26 novembre 2015 - 11:55:56
Dernière modification le : jeudi 28 juin 2018 - 18:44:03

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Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale. Testing PUF-Based Secure Key Storage Circuits. DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. pp.1-6, 2014, Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. 〈10.7873/DATE.2014.207〉. 〈lirmm-01234141〉

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