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Handling Exceptions in Petri Net-Based Digital Architecture: From Formalism to Implementation on FPGAs

Hélène Leroux 1 David Andreu 1 Karen Godary-Dejean 1 
1 CAMIN - Control of Artificial Movement and Intuitive Neuroprosthesis
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, CRISAM - Inria Sophia Antipolis - Méditerranée
Abstract : A component-based approach to the specification and implementation of complex digital systems on field-programmable gate arrays (FPGAs) has been developed, with the behavior and composition of the components specified by Petri nets (PNs). Yet modeling behavior in the case of error becomes intricate if only PNs are used. In this case, the designer often has to address every possible situation when an error occurs, which leads to complex models and human errors. This paper offers a way to model exception handling by adding the concept of macroplace (MP) to the formalism while preserving the conformity and efficiency of the implementation on a programmable logic device (such as FPGAs), as well as the analyzability of the model.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01241168
Contributor : Karen Godary-Dejean Connect in order to contact the contributor
Submitted on : Thursday, December 17, 2015 - 3:17:05 PM
Last modification on : Friday, August 5, 2022 - 10:53:05 AM

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Hélène Leroux, David Andreu, Karen Godary-Dejean. Handling Exceptions in Petri Net-Based Digital Architecture: From Formalism to Implementation on FPGAs. IEEE Transactions on Industrial Informatics, 2015, 11 (4), pp.897-906. ⟨10.1109/TII.2015.2435696⟩. ⟨lirmm-01241168⟩

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