On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

Charles Effiong 1 Vianney Lapotre 2 Abdoulaye Gamatié 1 Gilles Sassatelli 1 Aida Todri-Sanial 3 Khalid Latif 1
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248588
Contributor : Aida Todri-Sanial <>
Submitted on : Sunday, December 27, 2015 - 9:41:21 PM
Last modification on : Thursday, October 17, 2019 - 12:36:17 PM

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Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, et al.. On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.579-584, ⟨10.1109/ISVLSI.2015.49⟩. ⟨lirmm-01248588⟩

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