On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

Abstract : Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.
Type de document :
Communication dans un congrès
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.579-584, 2015, 〈10.1109/ISVLSI.2015.49〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248588
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:21
Dernière modification le : jeudi 14 juin 2018 - 01:20:02

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Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, et al.. On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.579-584, 2015, 〈10.1109/ISVLSI.2015.49〉. 〈lirmm-01248588〉

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