On the Performance Exploration of 3D NoCs with Resistive-Open TSVs - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2015

On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

Charles Emmanuel Effiong
Vianney Lapotre
Abdoulaye Gamatié
Gilles Sassatelli
Aida Todri-Sanial
Khalid Latif
  • Function : Author

Abstract

Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.
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lirmm-01248588 , version 1 (27-12-2015)

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Charles Emmanuel Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, et al.. On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. ISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.579-584, ⟨10.1109/ISVLSI.2015.49⟩. ⟨lirmm-01248588⟩
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