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Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Abstract : Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the most advanced perpendicular magnetic anisotropy (PMA) STT-MRAM for on-chip cache design in terms of performance, area and power consumption perspectively. The experimental results show that PMA STT-MRAM has higher power efficiency compared to SRAM as well as desirable scalability with technology node shrinking.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248593
Contributor : Aida Todri-Sanial <>
Submitted on : Wednesday, July 17, 2019 - 4:28:21 PM
Last modification on : Wednesday, September 16, 2020 - 5:22:26 PM

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Xiaolong Zhang, Yuanqing Cheng, Weisheng Zhao, Youguang Zhang, Aida Todri-Sanial. Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design. ICSICT: International Conference on Solid-State and Integrated Circuit Technology, Oct 2014, Guilin, China. ⟨10.1109/ICSICT.2014.7021342⟩. ⟨lirmm-01248593⟩

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