Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design
Abstract
Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the most advanced perpendicular magnetic anisotropy (PMA) STT-MRAM for on-chip cache design in terms of performance, area and power consumption perspectively. The experimental results show that PMA STT-MRAM has higher power efficiency compared to SRAM as well as desirable scalability with technology node shrinking.
Keywords
in-plane magnetic anisotropy effect
on-chip cache design
perpendicular magnetic anisotropy STT-MRAM
Permeability
Random access memory
Materials
Magnetic tunneling
technology node shrinking
Power efficiency
elevated power consumption
advanced PMA STT-MRAM
STT-MRAM-based architecture level evaluations
CMOS integrated circuits
Perpendicular magnetic anisotropy
integrated circuit design
cache storage
MRAM devices
CMOS memory circuits
Saturation magnetization
Switches
Transistors
| Origin | Files produced by the author(s) |
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