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HAL-LIRMM - Open Archive |  |
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults
Abstract : CMOS technology trends at one side open up some opportunities like making small and power efficient devices available, which in turn allow to put more functionality into a single chip. However, on the other side it poses some challenges like making devices vulnerable to hard and soft errors. In this paper we propose an efficient fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipeline structures. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies are running in parallel while the third one remains in standby until an error is detected. We implement this approach on a MIPS microprocessor as case study to make it resilient against transient and permanent faults.
Keywords :
Microprocessor
Hard errors
fault-tolerant architecture
Combinational logic protection
MIPS microprocessor
Computer architecture
Circuit faults
power efficient devices
Soft errors
Transient faults
pipelined microprocessor cores
transient and permanent faults
redundancy
combinational logic
Transient analysis
Pipelines
Microprocessors
Fault tolerant systems
Fault tolerance
CMOS technology
Microprocessor chips
Combinational circuits
CMOS logic circuits
Permanent faults
Pipeline structures
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248598
Contributor : Aida Todri-Sanial <>
Submitted on : Sunday, December 27, 2015 - 9:41:34 PM
Last modification on : Wednesday, December 11, 2019 - 1:32:02 AM
Contributor : Aida Todri-Sanial <>
Submitted on : Sunday, December 27, 2015 - 9:41:34 PM
Last modification on : Wednesday, December 11, 2019 - 1:32:02 AM
