Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults
Résumé
CMOS technology trends at one side open up some opportunities like making small and power efficient devices available, which in turn allow to put more functionality into a single chip. However, on the other side it poses some challenges like making devices vulnerable to hard and soft errors. In this paper we propose an efficient fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipeline structures. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies are running in parallel while the third one remains in standby until an error is detected. We implement this approach on a MIPS microprocessor as case study to make it resilient against transient and permanent faults.
Mots clés
CMOS technology
Fault tolerance
Fault tolerant systems
Microprocessors
Transient faults
Circuit faults
Computer architecture
MIPS microprocessor
Combinational logic protection
fault-tolerant architecture
Hard errors
Microprocessor chips
Combinational circuits
CMOS logic circuits
Permanent faults
Pipeline structures
pipelined microprocessor cores
power efficient devices
Soft errors
Pipelines
Transient analysis
combinational logic
redundancy
transient and permanent faults
Microprocessor