Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce

Anu Asokan 1 Aida Todri-Sanial 1 Alberto Bosio 1 Luigi Dilillo 1 Patrick Girard 1 Serge Pravossoudovitch 1 Arnaud Virazel 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Physical Design (PD) issues are becoming a major challenge with technology scaling in integrated circuits. Multi-aggressor crosstalk, power supply noise and ground bounce are some of the PD issues that cause considerable path delay variations. Therefore, these PD issues need to be considered during path delay testing to ensure better delay defect coverage. In this paper, we first show that the path delay Automatic Test Pattern Generation (ATPG) test methods are incapable of generating an input pattern that can capture worst-case path delay in circuits. We, then present our Physical Design Aware Pattern Generation (PDAPG) method to generate an input test pattern that can capture worst-case path delay in the presence of PD issues. We propose a backtrace X-filling approach to identify the relevant X-bits causing worst-case path delay. Simulations performed on ITC'99 benchmark circuits show that our PDAPG method is capable of providing high quality input test patterns in comparison with conventional path delay ATPG test methods.
Type de document :
Communication dans un congrès
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.207-212, 2014, 〈10.1109/DDECS.2014.6868791〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248599
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:35
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. IEEE, Design and Diagnostics of Electronic Circuits & Systems, 17th International Symposium on, pp.207-212, 2014, 〈10.1109/DDECS.2014.6868791〉. 〈lirmm-01248599〉

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