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Communication Dans Un Congrès Année : 2014

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce

Résumé

Physical Design (PD) issues are becoming a major challenge with technology scaling in integrated circuits. Multi-aggressor crosstalk, power supply noise and ground bounce are some of the PD issues that cause considerable path delay variations. Therefore, these PD issues need to be considered during path delay testing to ensure better delay defect coverage. In this paper, we first show that the path delay Automatic Test Pattern Generation (ATPG) test methods are incapable of generating an input pattern that can capture worst-case path delay in circuits. We, then present our Physical Design Aware Pattern Generation (PDAPG) method to generate an input test pattern that can capture worst-case path delay in the presence of PD issues. We propose a backtrace X-filling approach to identify the relevant X-bits causing worst-case path delay. Simulations performed on ITC'99 benchmark circuits show that our PDAPG method is capable of providing high quality input test patterns in comparison with conventional path delay ATPG test methods.
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Dates et versions

lirmm-01248599 , version 1 (27-12-2015)

Identifiants

Citer

Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.207-212, ⟨10.1109/DDECS.2014.6868791⟩. ⟨lirmm-01248599⟩
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