Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce
Résumé
Physical Design (PD) issues are becoming a major challenge with technology scaling in integrated circuits. Multi-aggressor crosstalk, power supply noise and ground bounce are some of the PD issues that cause considerable path delay variations. Therefore, these PD issues need to be considered during path delay testing to ensure better delay defect coverage. In this paper, we first show that the path delay Automatic Test Pattern Generation (ATPG) test methods are incapable of generating an input pattern that can capture worst-case path delay in circuits. We, then present our Physical Design Aware Pattern Generation (PDAPG) method to generate an input test pattern that can capture worst-case path delay in the presence of PD issues. We propose a backtrace X-filling approach to identify the relevant X-bits causing worst-case path delay. Simulations performed on ITC'99 benchmark circuits show that our PDAPG method is capable of providing high quality input test patterns in comparison with conventional path delay ATPG test methods.
Mots clés
PD issues
power supply circuits
PDAPG method
backtrace X-filling approach
delay defect coverage
ground bounce
input test patterns
integrated circuits
multiaggressor crosstalk
path delay ATPG test methods
path delay testing
path delay variations
physical design aware pattern generation method
physical design issues
power supply noise
Automatic test pattern generation
Crosstalk
Delays
Integrated circuit interconnections
Logic gates
SPICE
ITC'99 benchmark circuits
multi-aggressor crosstalk
integrated circuit noise
integrated circuit design
automatic test pattern generation test methods
X-bit filling
integrated circuit testing
automatic test pattern generation (ATPG)