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Conference Papers Year : 2015

Statistical Energy Study for 28nm FDSOI Technology

Rida Kheirallah
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Gilles R. Ducharme
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Nadine Azemard


Due to the effects of the Moore’s law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On-Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.
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lirmm-01256280 , version 1 (14-01-2016)


  • HAL Id : lirmm-01256280 , version 1


Rida Kheirallah, Gilles R. Ducharme, Nadine Azemard. Statistical Energy Study for 28nm FDSOI Technology. VARI: Workshop on CMOS Variability, Sep 2015, Salvador, Bahia, Brazil. ⟨lirmm-01256280⟩
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