An effective ATPG flow for Gate Delay Faults

Abstract : This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of Transition Delay (TD) Faults, and exploiting this relationship to produce effective patterns. The approach encompasses several steps: once a Gate Delay Fault is translated into a set of equivalent Transition Delay Faults, a traditional ATPG procedure can be used to determine patterns without any explicit timing information. The latter may account for several iterations, and it is returning the minimum delay that is detected for each delay faults. Effectiveness and feasibility of the proposed ATPG flow have been demonstrated on ISCAS'89 and ITC'99 benchmarks.
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Communication dans un congrès
DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, pp.1-6, 2015, 〈http://www.dtis2015.teiath.gr/〉. 〈10.1109/DTIS.2015.7127350〉
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Soumis le : mardi 17 mai 2016 - 14:38:19
Dernière modification le : jeudi 24 mai 2018 - 15:59:25

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Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, et al.. An effective ATPG flow for Gate Delay Faults. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. Design Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, pp.1-6, 2015, 〈http://www.dtis2015.teiath.gr/〉. 〈10.1109/DTIS.2015.7127350〉. 〈lirmm-01272719〉

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