Fault-tolerant architectures have been widely used in industry to prevent circuit reliability from becoming a bottleneck for the development of robust high-performance and low-power systems. One such solution is a Hybrid Fault-Tolerant Architecture that offers benefits such as low power and lifetime reliability improvement. However, it has been identified that there is room of improvement in efficiency. Thus, in this paper we present design space exploration and optimization of the Hybrid Fault-Tolerant Architecture. The study involves application of four design variants to some ITC benchmark circuits as case study. Experimental results compare the initial and optimized designs and show that the proposed optimizations offer around 65% reduction in terms of area, about 55% power saving and 87% less performance overhead as compared to the initial design without any penalty of the fault tolerance capability.