With technology scaling, the growing impact of signal integrity issues imposes significant challenges in integrated circuit testing. They cause delay in the supply and ground networks, cross talk noise between multiple interconnects, variations in substrate and thermal noise parameters of the circuit, etc. Therefore, the consideration of signal integrity issues during pattern generation ensures a better path delay fault coverage. In this paper, we propose a constrained Automatic Test Pattern Generation(ATPG) flow to test path delay fault by simultaneously coupling multiple aggressors surrounding a delay sensitive victim path. This flow uses the most effective aggressors for pattern generation based on cross talk information predetermined from the layout of the circuit. We developed the constrained ATPG flow by customizing the existing scan-based techniques to generate functionally testable path delay faults. The proposed ATPG flow is applied to ITC'99 benchmark circuits. The comparison results with SPICE-based simulations shows the effectiveness of our pattern in determining worst-case path delay and also in terms of computation time.