Spintronic Memory-Based Reconfigurable Computing

Abstract : Reconfigurable computing provides a number of advantages such as low Research and Development (R&D) cost and design flexibility when compared to application specific logic circuits (ASLC). However its low power efficiency greatly limits its applications. One of the major reasons of this shortcoming is that Static Random Access Memory (SRAM)-based configuration memory occupies a large die area and consumes high static power. The later is more severe due to the rapidly increasing leakage currents, which are intrinsic and become worse following the fabrication node shrinking. Spintronic memories (e.g., STT-MRAM and racetrack memory (RM)) are emerging nonvolatile memory technologies under intense investigation by both academics and industries. They promise ultra-high storage density, nonvolatility and low power. In this paper, we review the current status of spintronic memories for reconfigurable computing, the related device-circuit-system design requirements and present its perspectives. Mixed simulations based on spintronic device compact models show its high density and low power performance when compared to conventional SRAM-based reconfigurable computing.
Type de document :
Article dans une revue
SPIN, World Scientific Publishing, 2013, 3 (4), pp.1340010. 〈10.1142/S2010324713400109〉
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01306317
Contributeur : Caroline Lebrun <>
Soumis le : vendredi 22 avril 2016 - 17:52:02
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

Identifiants

Citation

Weisheng Zhao, Raphael M. Brum, Lionel Torres, Jacques-Olivier Klein, Gilles Sassatelli, et al.. Spintronic Memory-Based Reconfigurable Computing. SPIN, World Scientific Publishing, 2013, 3 (4), pp.1340010. 〈10.1142/S2010324713400109〉. 〈lirmm-01306317〉

Partager

Métriques

Consultations de la notice

52