Cache- and register-aware system reliability evaluation based on data lifetime analysis

Maha Kooli 1 Firas Kaddachi 1 Giorgio Di Natale 1 Alberto Bosio 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact product time-to-market. This paper introduces a new approach to evaluate, at early design phase, the reliability of a computing system running a software. The approach can be used when the hardware architecture is not completely defined yet. In order to be independent of the hardware architecture and at the same time accurate, we propose to use the Low-Level Virtual Machine (LLVM) framework. In addition, to reduce the reliability evaluation time, our approach consists in analyzing the variable lifetimes to compute the probability of masked faults. Finally, to achieve a better characterization we propose to consider also the presence of caches and register files. For this purpose, a cache emulator as well as a register file emulator are developed. Simulations run with our approach produce very similar results to those run with a hardware-based fault injector. This proves the accuracy of our approach to evaluate system reliability with a gain in the simulation time and without requiring a hardware platform.
Type de document :
Communication dans un congrès
VTS: VLSI Test Symposium , Apr 2016, Las Vegas, United States. 34th IEEE VLSI Test Symposium, 2016, 〈http://www.tttc-vts.org/public_html/new/2016/〉. 〈10.1109/VTS.2016.7477299〉
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01374569
Contributeur : Giorgio Di Natale <>
Soumis le : vendredi 30 septembre 2016 - 16:18:50
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

Identifiants

Collections

Citation

Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio. Cache- and register-aware system reliability evaluation based on data lifetime analysis. VTS: VLSI Test Symposium , Apr 2016, Las Vegas, United States. 34th IEEE VLSI Test Symposium, 2016, 〈http://www.tttc-vts.org/public_html/new/2016/〉. 〈10.1109/VTS.2016.7477299〉. 〈lirmm-01374569〉

Partager

Métriques

Consultations de la notice

40