A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring

Abstract : The emergence of power as a first-class design constraint has fueled the proposal of a growing number of optimization techniques, seeking the best trade-off to reach the maximum energy efficiency. Effective adaptation strategies depend critically on the monitoring method as an incorrect assessment of the system’s state will result in poor decision making. Yet it is indeed a fundamental issue: how to get a precise estimation of the system’s state, and especially in a cost-effective way? We address this question for the self-observation of the power consumption. We develop a method that combines several data mining algorithms to monitor the toggling activity on a few relevant signals selected at the RT-level. Our approach is based on a generic flow that is able to produce a power model for any RTL circuit on any technology. This contribution is evaluated on a System on Chip (SoC) RTL model implemented on an FPGA technology. The experiments demonstrate that the proposed method achieves the accuracy of analog power sensors (error lower than 1%) at a finer granularity and in a cost-effective way.