An SEU Tolerant MRAM based non-volatile asynchronous circuit design

Abstract : This work proposes a novel SEU tolerant circuit design based on asynchronous communica- tion coupled with magnetic memory, MRAM, and SOI process that can detect and correct single or multiple errors without triplication of the circuit.
Type de document :
Communication dans un congrès
RADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Bremen, Germany. 16th European Conference on Radiation and Its Effects on Components and Systems, 2016, 〈http://www.radecs2016.com/〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01396984
Contributeur : Lionel Torres <>
Soumis le : mardi 15 novembre 2016 - 11:53:07
Dernière modification le : vendredi 9 mars 2018 - 16:38:03

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  • HAL Id : lirmm-01396984, version 1

Citation

Jeremy Lopes, Gregory Dipendina, Edith Beigne, Lionel Torres. An SEU Tolerant MRAM based non-volatile asynchronous circuit design. RADECS: Radiation and Its Effects on Components and Systems, Sep 2016, Bremen, Germany. 16th European Conference on Radiation and Its Effects on Components and Systems, 2016, 〈http://www.radecs2016.com/〉. 〈lirmm-01396984〉

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