An SEU Tolerant MRAM based non-volatile asynchronous circuit design

Jeremy Lopes 1, 2 Gregory Dipendina 3 Edith Beigné 4 Lionel Torres 2
1 SPINTEC - SPINtronique et TEchnologie des Composants
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 CMP - Circuits Multi-Projets
4 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
Abstract : This work proposes a novel SEU tolerant circuit design based on asynchronous communica- tion coupled with magnetic memory, MRAM, and SOI process that can detect and correct single or multiple errors without triplication of the circuit.
Document type :
Conference papers
Complete list of metadatas
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01396984
Contributor : Lionel Torres <>
Submitted on : Tuesday, November 15, 2016 - 11:53:07 AM
Last modification on : Friday, September 13, 2019 - 8:38:02 PM

Identifiers

Collections

LIRMM | CNRS | SYSMIC | INAC-SPINTEC | CEA | DRT | UGA | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER | CEA-DRF | LETI | ADAC | IRIG | CEA-GRE

Citation

Jeremy Lopes, Gregory Dipendina, Edith Beigné, Lionel Torres. An SEU Tolerant MRAM based non-volatile asynchronous circuit design. RADECS: Radiation and its Effects on Components and Systems, Sep 2016, Bremen, Germany. ⟨10.1109/RADECS.2016.8093151⟩. ⟨lirmm-01396984⟩

Export

BibTeX TEI DC DCterms EndNote

Share

Metrics

Record views

441

Contact

Informations

CCSD