An SEU Tolerant MRAM based non-volatile asynchronous circuit design - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2016

An SEU Tolerant MRAM based non-volatile asynchronous circuit design

Abstract

This work proposes a novel SEU tolerant circuit design based on asynchronous communica- tion coupled with magnetic memory, MRAM, and SOI process that can detect and correct single or multiple errors without triplication of the circuit.
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Dates and versions

lirmm-01396984 , version 1 (15-11-2016)

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Jeremy Lopes, Gregory Dipendina, Edith Beigné, Lionel Torres. An SEU Tolerant MRAM based non-volatile asynchronous circuit design. RADECS: Radiation and its Effects on Components and Systems, Sep 2016, Bremen, Germany. ⟨10.1109/RADECS.2016.8093151⟩. ⟨lirmm-01396984⟩
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