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An SEU Tolerant MRAM based non-volatile asynchronous circuit design

Jeremy Lopes 1, 2 Gregory Dipendina 3 Edith Beigné 4 Lionel Torres 2
1 SPINTEC - SPINtronique et TEchnologie des Composants
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
3 CMP - Circuits Multi-Projets
4 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information
Abstract : This work proposes a novel SEU tolerant circuit design based on asynchronous communica- tion coupled with magnetic memory, MRAM, and SOI process that can detect and correct single or multiple errors without triplication of the circuit.
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01396984
Contributor : Lionel Torres <>
Submitted on : Tuesday, November 15, 2016 - 11:53:07 AM
Last modification on : Friday, November 6, 2020 - 4:19:16 AM

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LIRMM | CNRS | SYSMIC | INAC-SPINTEC | CEA | DRT | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER | CEA-DRF | LETI | ADAC | IRIG | CEA-GRE | UGA

Citation

Jeremy Lopes, Gregory Dipendina, Edith Beigné, Lionel Torres. An SEU Tolerant MRAM based non-volatile asynchronous circuit design. RADECS: Radiation and its Effects on Components and Systems, Sep 2016, Bremen, Germany. ⟨10.1109/RADECS.2016.8093151⟩. ⟨lirmm-01396984⟩

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