Multi-level MPSoC modeling for reducing software development cycle

Abstract : Multiprocessor SoCs (MPSoCs) have rapidly evolved towards high-performance heterogeneous computing systems designed under performance, power efficiency and scalability concerns. Such systems accomplish billions of operations per second moving towards hundreds of processing elements that communicate through a network-on-chip. The hardware and software complexity of such systems is increasing dramatically, resulting in new design challenges, such as providing scalable modeling facilities and verification for both hardware and software. This work proposes a multi-level design approach for MPSoCs, targeting the reduction of software development cycle. The paper also presents different scenarios for exploration purposes, showing the benefits in term of design space exploration for to the proposed environment.
Type de document :
Poster
ICECS: International Conference on Electronics, Circuits, and Systems, Dec 2013, Abu Dhabi, United Arab Emirates. 20th IEEE International Conference on Electronics, Circuits, and Systems, pp.489-492, 2013, 〈10.1109/ICECS.2013.6815460〉
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01419123
Contributeur : Gilles Sassatelli <>
Soumis le : dimanche 18 décembre 2016 - 20:08:16
Dernière modification le : jeudi 28 juin 2018 - 15:11:59

Identifiants

Collections

Citation

Marcelo Mandelli, Felipe Da Rosa, Luciano Ost, Gilles Sassatelli, Fernando G. Moraes. Multi-level MPSoC modeling for reducing software development cycle. ICECS: International Conference on Electronics, Circuits, and Systems, Dec 2013, Abu Dhabi, United Arab Emirates. 20th IEEE International Conference on Electronics, Circuits, and Systems, pp.489-492, 2013, 〈10.1109/ICECS.2013.6815460〉. 〈lirmm-01419123〉

Partager

Métriques

Consultations de la notice

286