Multi-level MPSoC modeling for reducing software development cycle
Résumé
Multiprocessor SoCs (MPSoCs) have rapidly evolved towards high-performance heterogeneous computing systems designed under performance, power efficiency and scalability concerns. Such systems accomplish billions of operations per second moving towards hundreds of processing elements that communicate through a network-on-chip. The hardware and software complexity of such systems is increasing dramatically, resulting in new design challenges, such as providing scalable modeling facilities and verification for both hardware and software. This work proposes a multi-level design approach for MPSoCs, targeting the reduction of software development cycle. The paper also presents different scenarios for exploration purposes, showing the benefits in term of design space exploration for to the proposed environment.
Mots clés
computational complexity
integrated circuit design
multiprocessing systems
system-on-chip
design space exploration
hardware complexity
high-performance heterogeneous computing systems
multilevel MPSoC modeling
multilevel design approach
multiprocessor SoC
network-on-chip
power efficiency
scalability concerns
software complexity
software development cycle reduction
Computer architecture
Debugging
Hardware
Load modeling
Nickel
Registers
Software
NoC-based MPSoCs
design space exploration of MPSoCs
dynamic mapping
modeling