Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing

Abstract : Embedded systems need ever increasing computational performances. Since they have limited energy resources, power consumption has to be minimized. Dynamic Voltage and Frequency Scaling (DVFS) techniques combined with Body Biasing techniques decrease the power consumption of a chip by providing just enough computational performance to the chip so as to finish the task at its deadline. A Power Mode (PM) is defined with the clock frequency F applied to the chip and the power P consumed by the chip. Executing tasks with the 2 neighbor frequencies of the target frequency should minimize the power consumption. Unfortunately, this choice is not always optimal since the set of available PMs may not fulfil the convexity property anymore when 3 actuators are considered. Here, a method is proposed to tackle this issue. PMs are selected to form a discretely convex subset. Results for a ring oscillator in FD-SOI exemplify that the proposed approach can save power consumption.
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Communication dans un congrès
PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.199-206, 2013, 〈10.1109/PATMOS.2013.6662174〉
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Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigne, Pascal Benoit, et al.. Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.199-206, 2013, 〈10.1109/PATMOS.2013.6662174〉. 〈lirmm-01421006〉

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