Power management through DVFS and dynamic body biasing in FD-SOI circuits

Abstract : The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%.
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Communication dans un congrès
DAC: Design Automation Conference, Jun 2014, San Francisco, United States. 51st Annual Design Automation Conference, pp.1-6, 2014, 〈10.1145/2593069.2593185〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01421009
Contributeur : Caroline Lebrun <>
Soumis le : mercredi 21 décembre 2016 - 13:48:31
Dernière modification le : lundi 24 septembre 2018 - 10:56:04

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Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro-Panades, et al.. Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC: Design Automation Conference, Jun 2014, San Francisco, United States. 51st Annual Design Automation Conference, pp.1-6, 2014, 〈10.1145/2593069.2593185〉. 〈lirmm-01421009〉

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