Power management through DVFS and dynamic body biasing in FD-SOI circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2014

Power management through DVFS and dynamic body biasing in FD-SOI circuits

Abstract

The emerging SOI technologies provide an increased body bias range compared to traditional bulk technologies, opening new opportunities. From the power management perspective, a new degree of freedom is added to the supply voltage and clock frequency variation, increasing the complexity of the power optimization problem. In this paper, a method is proposed to manage the power consumed in an FD-SOI circuit through supply and body bias voltages, and clock frequency variation. Results for a Digital Signal Processor in STMicroelectronics 28nm FD-SOI technology show that the power reduction ratio can reach 17%.
No file

Dates and versions

lirmm-01421009 , version 1 (21-12-2016)

Identifiers

Cite

Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro-Panades, et al.. Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC: Design Automation Conference, Jun 2014, San Francisco, United States. pp.1-6, ⟨10.1145/2593069.2593185⟩. ⟨lirmm-01421009⟩
223 View
0 Download

Altmetric

Share

Gmail Mastodon Facebook X LinkedIn More