Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs

Pierre-Yves Péneau 1 Rabab Bouziane 2 Abdoulaye Gamatié 1 Erven Rohou 2 Florent Bruguier 1 Gilles Sassatelli 1 Lionel Torres 1 Sophiane Senni 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : Energy-efficiency is one of the most challenging design issues in both embedded and high-performance computing domains. The aim is to reduce as much as possible the energy consumption of considered systems while providing them with the best computing performance. Finding an adequate solution to this problem certainly requires a cross-disciplinary approach capable of addressing the energy/performance trade-off at different system design levels. In this paper, we present an empirical impact analysis of the integration of Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) technologies in multicore architectures when applying some existing compiler optimizations. For that purpose, we use three well-established architecture and NVM evaluation tools: NVSim, gem5 and McPAT. Our results show that the integration of STT-MRAM at cache memory levels enables a significant reduction of the energy consumption (up to 24.2 % and 31 % on the considered multicore and monocore platforms respectively) while preserving the performance improvement provided by typical code optimizations. We also identify how the choice of the clock frequency impacts the relative efficiency of the considered memory technologies.
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PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.162-169, 2016, Proceedings of the 26th International Workshop on Power and Timing Modeling, Optimization and Simulation. 〈http://www.item.uni-bremen.de/patmos/〉. 〈10.1109/PATMOS.2016.7833682〉
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Soumis le : mercredi 20 juillet 2016 - 19:43:18
Dernière modification le : mercredi 11 avril 2018 - 01:51:18

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Pierre-Yves Péneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, et al.. Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.162-169, 2016, Proceedings of the 26th International Workshop on Power and Timing Modeling, Optimization and Simulation. 〈http://www.item.uni-bremen.de/patmos/〉. 〈10.1109/PATMOS.2016.7833682〉. 〈hal-01347354〉

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