Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study

Abstract : Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test issues. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage. The main goal of this paper is to investigate a methodology to improve the delay fault coverage of a given test set of functional test programs. We propose to exploit existing Design-for-Test architecture to apply in a smarter way the functional programs. Then, we combine those programs with the classical at-speed LOC and LOS delay fault testing schemes to further increase the delay fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage.
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Communication dans un congrès
ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, PA, United States. IEEE, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, pp.731-736, 2016, 〈10.1109/ISVLSI.2016.42 〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01446917
Contributeur : Caroline Lebrun <>
Soumis le : jeudi 26 janvier 2017 - 14:20:16
Dernière modification le : jeudi 28 juin 2018 - 18:44:05

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Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, et al.. Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, PA, United States. IEEE, VLSI (ISVLSI), 2016 IEEE Computer Society Annual Symposium on, pp.731-736, 2016, 〈10.1109/ISVLSI.2016.42 〉. 〈lirmm-01446917〉

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