An effective BIST architecture for power-gating mechanisms in low-power SRAMs

Alberto Bosio 1 Luigi Dilillo 1 Patrick Girard 1 Arnaud Virazel 1 Leonardo B. Zordan 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In low-power SRAMs, power-gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting-off one or more memory blocks (core-cell array, address decoder, I/O logic, etc), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we present an efficient Built-In-Self-Test architecture targeting defects affecting power-gating circuitry in low-power SRAMs. Experimental results show that the proposed solution improves the defect coverage and thus, it significantly increases the overall test quality compared to the state-of-the-art.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01457424
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Submitted on : Monday, February 6, 2017 - 2:29:24 PM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM

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Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo B. Zordan. An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED: International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.185-191, ⟨10.1109/ISQED.2016.7479198⟩. ⟨lirmm-01457424⟩

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