Exploration of magnetic memory for ultra low-power systems-on-chip

Guillaume Patrigeon 1 Sophiane Senni 1 Pascal Benoit 1 Lionel Torres 1
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Memories are currently a real bottleneck to design high speed, low area and energy-efficient systems-on-chip (SoC). An important proportion of total power is spent on memory systems. Ultra low-power (ULP) SoC often use different memory technologies to keep the advantages of each one (area, energy consumption, latency and non-volatility), however there are still penalties and this add more complexity at every development levels. MRAM (Magnetic Random Access Memory) is seen as a promising alternative solution to replace both traditional SRAM (Static Random Access Memory) and NVM (Non Volatile Memory), thanks to its high density, low read/right latency, non-volatility and negligible leakage current. The aim of this work is to explore the possibilities of using MRAM in ULP SoC at various memory levels.
Document type :
Poster communications
Complete list of metadatas

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01548980
Contributor : Guillaume Patrigeon <>
Submitted on : Wednesday, June 28, 2017 - 11:59:19 AM
Last modification on : Tuesday, March 26, 2019 - 11:06:20 AM

Identifiers

  • HAL Id : lirmm-01548980, version 1

Collections

Citation

Guillaume Patrigeon, Sophiane Senni, Pascal Benoit, Lionel Torres. Exploration of magnetic memory for ultra low-power systems-on-chip. Colloque GDR SoC-SiP, Jun 2017, Bordeaux, France. 12ème Colloque du GDR SoC/SiP, 2017, ⟨http://www.gdr-soc.cnrs.fr/colloques/colloque-2017/⟩. ⟨lirmm-01548980⟩

Share

Metrics

Record views

217

Files downloads

168