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Programmable volatile/non-volatile memory cell

Yoann Guillemenet 1 Lionel Torres 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01688122
Contributor : Caroline Lebrun <>
Submitted on : Friday, January 19, 2018 - 10:21:51 AM
Last modification on : Thursday, June 28, 2018 - 3:12:05 PM

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  • HAL Id : lirmm-01688122, version 1

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Citation

Yoann Guillemenet, Lionel Torres. Programmable volatile/non-volatile memory cell. United States, Patent n° : US20140050012 A1. 2014. ⟨lirmm-01688122⟩

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