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Combined volatile and non-volatile memory cell

Yoann Guillemenet 1 Lionel Torres 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD ); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; a first resistance switching element (202) coupled between said first storage node and a first access line (BL); and a second resistance switching element (204) coupled between said second storage node and a second access line (BLB).
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01688211
Contributor : Caroline Lebrun <>
Submitted on : Friday, January 19, 2018 - 11:06:14 AM
Last modification on : Tuesday, June 26, 2018 - 1:18:34 AM

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  • HAL Id : lirmm-01688211, version 1

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Citation

Yoann Guillemenet, Lionel Torres. Combined volatile and non-volatile memory cell. France, Patent n° : WO2012098182 (A1). 2012. ⟨lirmm-01688211⟩

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