Nowadays, power consumption is the one key factor that hinders System-on-Chip (SoC) performance. In order to reduce the power consumption, accurate and efficient power models have to be introduced early in the design flow, when most of the optimization potential is obtained. However, early accuracy cannot be ensured because of the lack of precise knowledge of the circuit structure. Current SoC design paradigm relies on Intellectual Property (IP) reuse, and low-level information about circuit components and structure is usually available. Thus, if we use this information and develop an estimation methodology that fits IP power modeling needs, the estimation accuracy at system level will be improved. This paper presents a Hybrid Power Estimation Technique (HPET). It is based on an effective library characterization methodology and an efficient hybrid power modeling approach to accurately and quickly assess gate-level power consumption. The aim is to give valuable and accurate physical information to design teams so they can ensure that the correct optimization techniques are implemented. Our approach can be used to compute both realistic instantaneous power and average power on a single simulation time. We performed experiments on different benchmark circuits synthesized using the 28nm FDSOI technology. To validate the proposed technique, we correlated our results with SPECTRE and PrimeTime-PX simulations. Our results showed that we can achieve up to 144× speedup on the simulation runtime with a mean error of about 6% and 13% for the instantaneous and average power components respectively.