High power consumption is a key factor hindering system-on-chip (SoC) performance. Accurate and efficient power models have to be introduced early in the design flow when most of the optimization potential is possible. However, early accuracy cannot be ensured because of the lack of precise knowledge of the final circuit structure. Current SoC design paradigm relies on intellectual property (IP) core reuse since low-level information about circuit components and structure is available. Thus, power estimation accuracy at the system level can be improved by using this information and developing an estimation methodology that fits IP cores power modeling needs. The main contribution of this paper is the development and validation of a hybrid power estimation technique (HPET), in which information coming from different abstraction levels is used to assess the power consumption in a fast and accurate manner. HPET is based on an effective characterization methodology of the technology library and an efficient hybrid power modeling approach. Experimental results, derived using HPET, have been validated on different benchmark circuits synthesized using the 28 nm “fully depleted silicon on insulator” (FDSOI) technology. Experimental results show that in average we can achieve up to 68× improvement in power estimation run-time while having transistor-level accuracy. For both analyzed power types (instantaneous and average), HPET results are well correlated with respect to the ones computed in SPECTRE and Primetime-PX. This demonstrates that HPET is an effective technique to enhance power macro-modeling creation at high abstraction levels.