Atomistic to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles IEEE Transactions on Nanotechnology Year : 2018

Atomistic to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects

Jie Liang
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  • PersonId : 971767
Reetu Raj Pandey
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Rongmei Chen
Asen Asenov
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Aida Todri-Sanial

Abstract

In this article, we present a hierarchical model for doped single-wall carbon nanotube (SWCNT) for on-chip interconnect application. We study the realistic CVD grown SWCNT with defects and contacts, which induce important resistance values and worsens SWCNT on-chip interconnect performance. We investigate the fundamental physical mechanism of doping in SWCNT with the purpose of improving its electrical conductivity as well as combining mitigating the effects of defects and large contact resistance. The atomistic model provides insights on statistical variations of the number of conducting channels of doped SWCNT and SWCNT resistance variation with a various number of vacancy defects configurations. Based on atomistic simulations, we develop circuit-level models to simulate SWCNT interconnects and understand the impact of doping, defects, and contacts. Simulation results show an 80% resistance reduction by doping. Additionally, we observe that doping can mitigate the effects of defects and limited impact on contact resistance.
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Dates and versions

lirmm-01795792 , version 1 (06-06-2019)

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Jie Liang, Jaehyun Lee, Salim Berrada, Vihar Georgiev, Reetu Raj Pandey, et al.. Atomistic to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects. IEEE Transactions on Nanotechnology, 2018, 17 (6), pp.1084-1088. ⟨10.1109/TNANO.2018.2802320⟩. ⟨lirmm-01795792⟩
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