A high-reliability and low-power computing-in-memory implementation within STT-MRAM - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Microelectronics Journal Year : 2018

A high-reliability and low-power computing-in-memory implementation within STT-MRAM


In the conventional Von-Neumann computer architecture, more energy and time are consumed by the data transport, rather than the computation itself because of the limited bandwidth between the processor and memory. Computing-in-memory (CIM) is therefore proposed to effectively address the issue by moving some specified kinds of computation into the memory. It has been proposed for several decades, however, not really used when considering the reliability and cost. With the emergence of non-volatile memories, the CIM has regained interest to tackle the issue. In this paper, we implement a CIM scheme: ComRef (Complementary Reference) within STT-MRAM (Spin Transfer Torque Magnetic Random-Access Memory), and then compare its reliability and performance with the DualRef (Dual Reference) CIM implementation. Simulation results reveal that the ComRef obviously improves the reliability by decreasing 67.1% of the operation error rate and by increasing up to 57.4% of the sensing margin. It accelerates the bitwise logic operation with cutting down 20.8% (∼41.1 ps) of the operation delay. Most importantly, it is highly energy efficient by reducing 23.4% of the average dynamic energy and 65.6% of the average static power. The ComRef provides a pathway to implement high-reliability and low-power CIM paradigm within STT-MRAM.
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lirmm-01880058 , version 1 (08-02-2019)



Liuyang Zhang, Erya Deng, Hao Cai, You Wang, Lionel Torres, et al.. A high-reliability and low-power computing-in-memory implementation within STT-MRAM. Microelectronics Journal, 2018, 81, pp.69-75. ⟨10.1016/j.mejo.2018.09.005⟩. ⟨lirmm-01880058⟩
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