This paper presents an original solution to the test scheduling problem for 3D stacked integrated circuits. We explore a session-less approach where the test procedure of any core can start at any time as long as Test Access Mechanisms (TAMs) are available and constraints in terms of power and thermal limits are respected. Given a set of test procedure with fixed length and a set of test resources (TAM width), we determine test procedure start times such that the system test time is minimized. The proposed greedy heuristic is applied on fully detailed benchmarks and is compared with solutions obtained from session-based approaches. The results show that the session-less solutions outperforms the session-based ones. This is so even though the session-based solution is optimal, which is generally not the case for scheduling solutions resulting from heuristics used for dealing with large systems.