Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS

David Novo; R. Fasthuber; P. Raghavan; A. Bourdoux; Min Li; L. van Der Perre; F. Catthoor

doi:10.1109/SIPS.2009.5336241

Conference Papers Year : 2009

Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS

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David Novo

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ORCID : 0000-0002-5510-4152
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R. Fasthuber

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P. Raghavan

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A. Bourdoux

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Min Li

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ORCID : 0000-0002-9428-626X

L. van Der Perre

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IMEC

F. Catthoor

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Computer Science [cs]

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-02089304

Submitted on : Wednesday, April 3, 2019-4:01:17 PM

Last modification on : Thursday, November 23, 2023-10:48:07 AM

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lirmm-02089304 , version 1 (03-04-2019)

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HAL Id : lirmm-02089304 , version 1
DOI : 10.1109/SIPS.2009.5336241

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David Novo, R. Fasthuber, P. Raghavan, A. Bourdoux, Min Li, et al.. Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS. IEEE Workshop on Signal Processing Systems (SiPS), Oct 2009, Tampere, Finland. pp.151-156, ⟨10.1109/SIPS.2009.5336241⟩. ⟨lirmm-02089304⟩

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Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS

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