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Conference papers

Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-02089304
Contributor : David Novo Connect in order to contact the contributor
Submitted on : Wednesday, April 3, 2019 - 4:01:17 PM
Last modification on : Thursday, July 7, 2022 - 4:37:30 AM

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David Novo, R. Fasthuber, P. Raghavan, A. Bourdoux, Min Li, et al.. Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS. IEEE Workshop on Signal Processing Systems (SiPS), Oct 2009, Tampere, Finland. pp.151-156, ⟨10.1109/SIPS.2009.5336241⟩. ⟨lirmm-02089304⟩

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