High level synthesis: a data path partitioning method dedicated to speed enhancement - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 1991

High level synthesis: a data path partitioning method dedicated to speed enhancement

Abstract

In the field of high level synthesis, a speed improvement of structural designs can be obtained by partitioning the physical data path of the behavioral compilers outcome. This speed improvement is achieved by increasing the number of operations treated simultaneously without appreciable overhead in the silicon area. The authors present a partitioning method based on bus splitting. This method makes use of hierarchical clustering and a description of all the measures needed for partitioning is given.
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Dates and versions

lirmm-02288876 , version 1 (19-03-2022)

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Fabrice Monteiro, Bruno Rouzeyre, Georges Sagnes. High level synthesis: a data path partitioning method dedicated to speed enhancement. EDAC 1991 - European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.123-128, ⟨10.1109/EDAC.1991.206374⟩. ⟨lirmm-02288876⟩
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