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High level synthesis: a data path partitioning method dedicated to speed enhancement

F. Monteiro Bruno Rouzeyre 1 Georges Sagnes
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In the field of high level synthesis, a speed improvement of structural designs can be obtained by partitioning the physical data path of the behavioral compilers outcome. This speed improvement is achieved by increasing the number of operations treated simultaneously without appreciable overhead in the silicon area. The authors present a partitioning method based on bus splitting. This method makes use of hierarchical clustering and a description of all the measures needed for partitioning is given.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-02288876
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Submitted on : Monday, September 16, 2019 - 10:37:23 AM
Last modification on : Tuesday, September 17, 2019 - 1:17:07 AM

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F. Monteiro, Bruno Rouzeyre, Georges Sagnes. High level synthesis: a data path partitioning method dedicated to speed enhancement. EDAC: European Conference on Design Automation, Feb 1991, Amsterdam, Netherlands. pp.123-128, ⟨10.1109/EDAC.1991.206374⟩. ⟨lirmm-02288876⟩

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