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Journal Articles Microelectronics Reliability Year : 2018

An efficient EDAC approach for handling multiple bit upsets in memory array

Abstract

Ionizing radiation and electromagnetic interference (EMI) can cause single event upset (SEU) in memory elements. This threat is one of the major concerns when considering the design of electronic systems for critical applications. Single Error Correction - Double Error Detection (SEC-DED) codes can be used to avoid data corruption caused by soft errors, protecting the memory against single errors. However, the presence of multiple bit upsets is becoming more frequent as technology scales down. Hereafter, we present an Error Detection and Correction (EDAC) approach, namely Parity per Byte and Duplication (PBD), to protect data stored in memory. The technique was described in VHDL, coupled with the LEON3 softcore processor, and mapped into a commercial FPGA. The obtained results have shown that the proposed approach is very effective to detect and correct multiple bit-flips in memory arrays.
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Dates and versions

lirmm-02420911 , version 1 (20-12-2019)

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Roger C. Goerl, Paulo R.C. Villa, Letícia Poehls, Eduardo Augusto Bezerra, Fabian Luis Vargas. An efficient EDAC approach for handling multiple bit upsets in memory array. Microelectronics Reliability, 2018, 88-90, pp.214-218. ⟨10.1016/j.microrel.2018.07.060⟩. ⟨lirmm-02420911⟩
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