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Design and Technology-level Optimization Challenges for Carbon Nanotube Circuits

Aida Todri-Sanial 1
1 SmartIES - Smart Integrated Electronic Systems
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This talk aims to give an in-depth look into the process, growth, characterization, modeling, and simulation of carbon nanotube as the back-end of line material for both local and global on-chip interconnects. The talk is organized into two parts. The first part provides an in-depth overview of the process and growth of carbon nanotubes and their resistance measurements [1-2, 11-12]. In the second part, the talk is dedicated to investigating carbon nanotubes for digital logic cells such as interconnects for signal, power and ground interconnect material [7-10,18-22]. Due to the low-temperature growth, carbon nanotubes inherit a lot of defects that worsen its electrical resistance and ballistics transport. We investigate the doping of CNTs and show both experimental and simulations results of doped CNTs and their improved resistance [3-6, 13-15, 17]. We compare the performance, power and area metrics of digital logics cells with conventional copper and carbon nanotube interconnects (undoped and doped) to highlight the advantages and limitations of carbon nanotube BEOL interconnects. This talk gives an overview of our group research results achieved in the EU H2020 CONNECT project.
Keywords : Carbon nanotube CNT
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Contributor : Aida Todri-Sanial <>
Submitted on : Tuesday, April 21, 2020 - 2:26:56 PM
Last modification on : Wednesday, April 22, 2020 - 1:44:34 AM


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  • HAL Id : lirmm-02549406, version 1


Aida Todri-Sanial. Design and Technology-level Optimization Challenges for Carbon Nanotube Circuits. International Workshop on Advanced Electronic Design Automation (EDA), Jan 2020, Xidian, China. ⟨lirmm-02549406⟩



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