Characterization of a RISC-V Microcontroller Through Fault Injection
Abstract
This article reports the results of fault injection on a microcontroller based on the RISC-V (Riscy) architecture. The fault injection approach uses fault simualation based on Modelsim and targets a set of 1000 fault injected per benchmark. The benchmarks were chosen to be representative of generic workloads but also to specific benchmarks applicable to embed- ded microcontroller in space applications.
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