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Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments

Abstract : With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-03031709
Contributor : Isabelle Gouat <>
Submitted on : Monday, November 30, 2020 - 3:46:47 PM
Last modification on : Tuesday, December 1, 2020 - 3:44:17 PM
Long-term archiving on: : Monday, March 1, 2021 - 7:35:00 PM

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Aibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui, Zhili Chen, et al.. Novel Quadruple-Node-Upset-Tolerant Latch Designs with Optimized Overhead for Reliable Computing in Harsh Radiation Environments. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, In press, ⟨10.1109/TETC.2020.3025584⟩. ⟨lirmm-03031709⟩

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