Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2020

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Tianming Ni
Jie Cui
Xiaoqing Wen

Abstract

In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.
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Origin : Publication funded by an institution

Dates and versions

lirmm-03033821 , version 1 (01-12-2020)

Identifiers

Cite

Zhengda Dou, Aibin Yan, Jun Zhou, Yuanjie Hu, Yan Chen, et al.. Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors. ITC-Asia 2020 - 4th International Test Conference in Asia, Sep 2020, Taipei, Taiwan. pp.35-40, ⟨10.1109/ITC-Asia51099.2020.00018⟩. ⟨lirmm-03033821⟩
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